1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device including a doping process.
2. Description of the Related Art
Generally, as a semiconductor device is more highly integrated, single elements constituting the semiconductor device (e.g., a field effect transistor (FET), a capacitor, an interconnection) are gradually scaled down in size. In particular, as the FET (hereinafter, referred to as a transistor in general) is scaled down, the driving current of the transistor decreases, which leads to a short channel effect or a drain induced barrier lowering (DIBL) effect. As a result, various characteristics of the semiconductor device may be degraded. For example, because the driving current amount decreases, the operational speed of the transistor may be lowered, and a margin that the memory device senses to identify data may be reduced. It is well known that transistor performance is degraded due to the short channel effect or the DIBL effect.
Recently, in order to address the problems of the transistor, a fin transistor has been proposed. The fin transistor employs a fin with a three-dimensional structure, which is protruded upward over a silicon substrate, as an active region. The fin transistor includes the fin, a gate electrode crossing over the fin, and a gate oxide layer interposed between the gate electrode and the gate oxide layer. Source/drain regions are formed on the fin disposed at both sides of the gate electrode.
A channel region of the fin transistor corresponds to the fin disposed under the gate electrode. That is, the channel region includes the top surface and both side surfaces of the fin under the gate electrode. This enables the driving current amount to increase because the width of the channel region increases in a restricted area. In addition, the gate electrode controls the channel region on both sides thereof to thereby enhance the controllability of the gate electrode with respect to the channel region. Therefore, it is possible to minimize the dergradation of the transistor characteristic by minimizing the short channel effect or the DIBL effect. The channel region of the fin transistor may be doped with n-type or p-type impurities in order to adjust the threshold voltage of the fin transistor. Typically, the impurities may be injected into the channel region of the fin transistor by an implantation process. In this implantation process, the impurity ions are anisotropically injected strongly as the projected range. As a result, the channel region of the fin transistor having the three-dimensional structure (hereinafter, referred to as a fin channel region) may be doped nonuniformly. In order to improve the doping uniformity for the fin channel region, the impurity ions may be injected by a tilted implantation. However, the impurity ions may be blocked by other adjacent fins or other structures, or the fin channel region may also be doped nonuniformly due to a restricted tilted angle. Accordingly, there is a problem that the nonuniform doping of the channel region causes the threshold voltage of the fin transistor to be varied, which results in degrading the characteristic of the fin transistor after all.